Forum Discussion
toczkows
New Contributor
3 years agoTimeQuest ALTPLL wrong setup relation
Hi,
recently I found some strange behaviour of timequest STA regarding simple design with PLL on Quartus Prime Lite. If there is simple data transfer between clock (i_CLK) and clock that's output ...
Nurina
Regular Contributor
3 years agoHello,
I see your problem now. I've tested on Pro as well and it works. Seems like this is a bug on Standard, I am reporting this problem to engineering team.
Regards,
Nurina