New Contributor
Regular ContributorHi,
Are you saying the PLL is launching/latching at the wrong edge? You can try set_multicycle_path for the PLL clock. https://www.intel.com/content/www/us/en/programmable/quartushelp/13.0/mergedProjects/tafs/tafs/tcl_pkg_sdc_ver_1.5_cmd_set_multicycle_path.htm
Regards,
Nurina
New ContributorThanks for your answer. MC can solve STA ts/th violations but doesn't anwser why STA ts/th in this example are dependant on arbitrary input clock phase shift (it can be any value), hance STA calculations looks wrong and completely unreliable.
