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toczkows
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3 years ago

TimeQuest ALTPLL wrong setup relation

Hi, recently I found some strange behaviour of timequest STA regarding simple design with PLL on Quartus Prime Lite. If there is simple data transfer between clock (i_CLK) and clock that's output ...
toczkows's avatar
toczkows
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3 years ago

Hi,

@Nurina wrote:

Hi,

Shifting a clock will change the setup and hold relationship because then the launch and latch edge will be changing. By default, TimeQuest will choose the nearest latch edge and this results in a different setup & hold relationship. If the setup & hold relationship calculated by TimeQuest is not what you want, you should use set_multicycle_path.

Regards,

Nurina


Question here was transfer between register A cloecked by "clock" and register B clocked by "clock" after PLL in normal mode. According to documentation

4.2.8.4. Normal Compensation Mode (intel.com) this clock is internally (inside FPGA) phase aligned to input clock - and thats not what TimeQuest is reporting - as you can see in previews screens. When using Quartus Pro or Vivado in this mode clock is always reported as phase alligned ( so setup is equal to period and hold to 0) but not in Quartus Prime for only some input phase cases. And my question is why ? Is it a bug in documentation for cycone V or in timequest or something different