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Altera_Forum
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15 years ago

Source Synchronous Analysis with TimeQuest

This is a plug, but I just added a document on source-synchronous timing analysis to the alterawiki:

http://www.alterawiki.com/wiki/source_synchronous_analysis_with_timequest

It is a companion guide to the TimeQuest User Guide I have up there(except this one has actual projects, and I want to add more...)

I had great difficulty with this one, as it was very difficult determining when too much information was provided or too little. (You'll see I erred on the side of too much). I would appreciate any feedback from anyone trying to use it for a real design. If you email me through this forum, please make sure you haven't disabled reply emails. Or just add to this thread. Thanks.

16 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    Awesome, thanks. I believe I can add a few sections pretty quickly and will incorporate your edits.

  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    I am using Case 2, FPGA is the receiver and does not phase-shift the clock. When running through the example, Quartus 12.0 SP 2.16 reports the following warning:

    Warning (15062): PLL "ssync_pll:inst1|altpll:altpll_component|ssync_pll_altpll:auto_generated|pll1" in Source Synchronous mode with compensated output clock set to clk[0] is not fully compensated because it does not feed an I/O input register

    This makes sense because the FF's for the DDR are not in the IOB, but is this warning safe to ignore? Would one expect to always see this warning when doing Source Synchronous DDR? Is there some way to add constraint to block the warning?

    I also see for all data lines:

    Warning (176441): The I/O pin ssync_rx_data[x] cannot meet the timing constraints due to conflicting requirements. The I/O pin is a PLL compensated I/O, but the setup/hold requirements are in conflict with the source PLL mode(source synchronous or ZDB ).

    Can this too be ignored?

    When in the TimeQuest, after running the provided TQ_analysis.tcl with no change to the provided examples I get hold timing violations. I would expect at the minimum that this report should show all passing. Is this expected?

    Thanks for the help
  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    Are you doing Cyclone III/IV, which doesn't have I/O input regs? If so, the first warning should be ignorable, since it can't put them in the I/O, as you state. I imagine that's a generic warning, that's saying, "You changed the PLL mode to ssync and I assume you want IO registers...". As long as it meets timing, ignore it.

    As for the second, I'm not quite sure what that means, but again, if you have correct timing constraints and meet timing, you should be fine.

    I just compiled Case 2 in Quartus(a build of 12.1 that will be released soon) and it met timing. Not sure what you're seeing. Is Case 2 the same thing you're doing in your design(frequency and external delays)?
  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    I found that I was running my modified constraints, once reverting back to the supplied example, timing is met and I only see the first warning.

    I am trying to get this interface to work at 350Mhz on both a cyclone 3 and 4, speed grade 7. I read one spot that mention DDR interfaces could reach 400Mhz so I thought this should work.

    To test it out I set my ext board delays to zero, to assume all FPGA delay, then set the clock to 350 MHz. That is what prompted the second error and failed timing.

    It appears that the I/O timing constraints are conflicting due to my high clock speed.

    Can you confirm what is the maximum DDR frequency assuming zero external delays?

    Thanks
  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    I was probably referring to Stratix IV devices. (It also always depends on the external device's skew, which is why it's hard to throw out single number). I took my sample design, changed it to a -7 and the clock speed to 350MHz. (This required changing the PLL and the .sdc lines:

    create_clock -period 2.857 -name ssync_rx_clk [get_ports ssync_rx_clk] -waveform {0.714 2.143}

    and:

    create_clock -period 2.857 -name ssync_clk_ext

    This creates a setup relationship of 0.714 and hold of -0.714. I also set the external delays to 0 for the time being. After compiling, the setup made timing by 777ps and hold failed by -293ps. Balancing those out, I tried to phase-shift the PLL output to -484ps(I was only able to do a shift of -357ps, or -45 degrees). It still failed timing. I haven't analyzed it any further, and sometimes playing around with the settings and placement can improve it some, and maybe it's just possible to meet timing(a big maybe), but that's still with the external delays at 0ns. In reality, they're going to be something that is going to hurt margin. I don't know how much skew there is, but imagine this speed isn't possible in this device.
  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    Thanks for the quick replies, that all makes sense.

    Referencing Table 1-36, “LVDS Receiver Timing Specification for Cyclone IV Devices” out of the Cyclone IV Device Data sheet. It indicates for a speed grade C6 the IO can run up to 437.5 Mhz. Is this assuming SDR and is capable of using the IOBFF and that is how the part can reach these high speeds?

    Is there any place in the Altera documentation that attempts to specify an equivalent table for DDR IO?
  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    --- Quote Start ---

    Thanks for the quick replies, that all makes sense.

    Referencing Table 1-36, “LVDS Receiver Timing Specification for Cyclone IV Devices” out of the Cyclone IV Device Data sheet. It indicates for a speed grade C6 the IO can run up to 437.5 Mhz. Is this assuming SDR and is capable of using the IOBFF and that is how the part can reach these high speeds?

    Is there any place in the Altera documentation that attempts to specify an equivalent table for DDR IO?

    --- Quote End ---

    I will assume that data rate of 437.5MHz is so irrespective of SDR or DDR since it is the rate that is "seen" and not on which clock edge does it occur and I will also assume that the IO register is used for such speed.

    Here I am separating the concept of register timing violation from io speed violation. Register timing limits speed but io limits it also through its toggle rate which normally is more than acheivable device fmax, otherwise you get restricted fmax as opposed to fmax.
  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    This is my understanding, please correct me if I'm wrong.

    I don't believe the data rate in Table 1-36 is irrespective of SDR and DDR if it assumes the IOB FF is used. In DDR two FF's are used to clock data, one running off the rising edge and one running of the falling edge. The IO architecture of the Cyclone 4 only has one embedded High Speed FF. So in order to achieve DDR the data signal has to leave the IOB and leverage two FF's in the fabric. The routing time for this is pretty significant. I believe the Table 1-36 is assuming the embedded FF is used by the term HSIODR. So at SDR the IO can acheive 875Mbps, but DDR would be much lower because of the added delay to use the FF's outside of the IOB. If this is correct it would be nice to see an equivalent table that lists out the data rates achievable by DDR.

    The part that I don't understand is the HSIODR is twice the clock frequencies so it does appear to assume DDR.

    Working through the Source Synchronous examples provided in the above links, and confirmed by Ryan S. 350Mhz DDR is not achievable on Cyclone 3. I ran the same examples on the Cyclone 4 and got similar results.

    I'm not too worried about my register timing, my PLL can hit 350 Mhz clocks and the data is going to quickly go to a FIFO and transition to lower register frequencies.

    Thanks for your input
  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    I looked at the table. The figures are given for the case of clock or data. Obviously the toggle rate of any clock is twice that of its data so the frequency of data looks double. I think the issue has nothing to do with fpga fabric. It is about io serdes receiver which expects a serial stream rather than data and clock. It then recovers clock from the serial stream and passes it to the fabric. This area of fpga is dedicated block for this purpose.