Source Synchronous Analysis with TimeQuest

I am using Case 2, FPGA is the receiver and does not phase-shift the clock. When running through the example, Quartus 12.0 SP 2.16 reports the following warning:

Warning (15062): PLL "ssync_pll:inst1|altpll:altpll_component|ssync_pll_altpll:auto_generated|pll1" in Source Synchronous mode with compensated output clock set to clk[0] is not fully compensated because it does not feed an I/O input register

This makes sense because the FF's for the DDR are not in the IOB, but is this warning safe to ignore? Would one expect to always see this warning when doing Source Synchronous DDR? Is there some way to add constraint to block the warning?

I also see for all data lines:

Warning (176441): The I/O pin ssync_rx_data[x] cannot meet the timing constraints due to conflicting requirements. The I/O pin is a PLL compensated I/O, but the setup/hold requirements are in conflict with the source PLL mode(source synchronous or ZDB ).

Can this too be ignored?

When in the TimeQuest, after running the provided TQ_analysis.tcl with no change to the provided examples I get hold timing violations. I would expect at the minimum that this report should show all passing. Is this expected?

Thanks for the help