Source Synchronous Analysis with TimeQuest

I found that I was running my modified constraints, once reverting back to the supplied example, timing is met and I only see the first warning.

I am trying to get this interface to work at 350Mhz on both a cyclone 3 and 4, speed grade 7. I read one spot that mention DDR interfaces could reach 400Mhz so I thought this should work.

To test it out I set my ext board delays to zero, to assume all FPGA delay, then set the clock to 350 MHz. That is what prompted the second error and failed timing.

It appears that the I/O timing constraints are conflicting due to my high clock speed.

Can you confirm what is the maximum DDR frequency assuming zero external delays?

Thanks