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Thanks for the quick replies, that all makes sense.
Referencing Table 1-36, “LVDS Receiver Timing Specification for Cyclone IV Devices” out of the Cyclone IV Device Data sheet. It indicates for a speed grade C6 the IO can run up to 437.5 Mhz. Is this assuming SDR and is capable of using the IOBFF and that is how the part can reach these high speeds?
Is there any place in the Altera documentation that attempts to specify an equivalent table for DDR IO?
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I will assume that data rate of 437.5MHz is so irrespective of SDR or DDR since it is the rate that is "seen" and not on which clock edge does it occur and I will also assume that the IO register is used for such speed.
Here I am separating the concept of register timing violation from io speed violation. Register timing limits speed but io limits it also through its toggle rate which normally is more than acheivable device fmax, otherwise you get restricted fmax as opposed to fmax.
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