Source Synchronous Analysis with TimeQuest

This is my understanding, please correct me if I'm wrong.

I don't believe the data rate in Table 1-36 is irrespective of SDR and DDR if it assumes the IOB FF is used. In DDR two FF's are used to clock data, one running off the rising edge and one running of the falling edge. The IO architecture of the Cyclone 4 only has one embedded High Speed FF. So in order to achieve DDR the data signal has to leave the IOB and leverage two FF's in the fabric. The routing time for this is pretty significant. I believe the Table 1-36 is assuming the embedded FF is used by the term HSIODR. So at SDR the IO can acheive 875Mbps, but DDR would be much lower because of the added delay to use the FF's outside of the IOB. If this is correct it would be nice to see an equivalent table that lists out the data rates achievable by DDR.

The part that I don't understand is the HSIODR is twice the clock frequencies so it does appear to assume DDR.

Working through the Source Synchronous examples provided in the above links, and confirmed by Ryan S. 350Mhz DDR is not achievable on Cyclone 3. I ran the same examples on the Cyclone 4 and got similar results.

I'm not too worried about my register timing, my PLL can hit 350 Mhz clocks and the data is going to quickly go to a FIFO and transition to lower register frequencies.

Thanks for your input