Source Synchronous Analysis with TimeQuest

I was probably referring to Stratix IV devices. (It also always depends on the external device's skew, which is why it's hard to throw out single number). I took my sample design, changed it to a -7 and the clock speed to 350MHz. (This required changing the PLL and the .sdc lines:

create_clock -period 2.857 -name ssync_rx_clk [get_ports ssync_rx_clk] -waveform {0.714 2.143}

and:

create_clock -period 2.857 -name ssync_clk_ext

This creates a setup relationship of 0.714 and hold of -0.714. I also set the external delays to 0 for the time being. After compiling, the setup made timing by 777ps and hold failed by -293ps. Balancing those out, I tried to phase-shift the PLL output to -484ps(I was only able to do a shift of -357ps, or -45 degrees). It still failed timing. I haven't analyzed it any further, and sometimes playing around with the settings and placement can improve it some, and maybe it's just possible to meet timing(a big maybe), but that's still with the external delays at 0ns. In reality, they're going to be something that is going to hurt margin. I don't know how much skew there is, but imagine this speed isn't possible in this device.