Source Synchronous Analysis with TimeQuest

Are you doing Cyclone III/IV, which doesn't have I/O input regs? If so, the first warning should be ignorable, since it can't put them in the I/O, as you state. I imagine that's a generic warning, that's saying, "You changed the PLL mode to ssync and I assume you want IO registers...". As long as it meets timing, ignore it.

As for the second, I'm not quite sure what that means, but again, if you have correct timing constraints and meet timing, you should be fine.

I just compiled Case 2 in Quartus(a build of 12.1 that will be released soon) and it met timing. Not sure what you're seeing. Is Case 2 the same thing you're doing in your design(frequency and external delays)?