[SignalTap] How to add signals defined as "wire" in RTL?

I'd like to add the pix_data_in_422 signal, to the SignalTap (signal definition please see below).

logic [PIX_DATA_BW-1:0] pix_data_in_422;
always_comb begin : pix_data_in_422_l
     pix_data_in_422 = {//[95:48]
                        pix_data_in[47+48:40+48],pix_data_in[15+48:12+48],4'd0,   // [47:32] Cr/Cb
                        pix_data_in[31+48:24+48],pix_data_in[11+48: 8+48],4'd0,   // [31:16] Y
                        16'd0,                                         // [15:0]
                        //[47:0]
                        pix_data_in[47:40],pix_data_in[15:12],4'd0,   // [47:32] Cr/Cb
                        pix_data_in[31:24],pix_data_in [11:8],4'd0,   // [31:16] Y
                        16'd0                                         // [15:0]
};
end

Here is the filter I applied in SignalTap:

Also with the per-synthesis filter, SignalTap cannot find the signal:

yes, I have re-run the Analysis & Elaboration - got the same result....

I cannot understand what's the problem with the signal ....

Tried to find this signal in the RTL Viewer as well... it doesn't present there!

But, this signal does present in the simulations and the design also works on the board - without this signal the design cannot work... But Quartus how some hides it from the SignalTap and RTL Viewer.... believable...

The file with the signal is a part of the project - I checked this 1000 times !!!

This is like a black magic!

I've added the "noprune" attribute to the problematic signal and also the "keep" attribute to another signal, which is driven by the problematic signal - nothing helps.... No one of them is visible neither in RTL Viewer nor in SignalTap .

Here is how I added the attributes:

logic [PIX_DATA_BW-1:0] pix_data_in_422 /* synthesis noprune */;
wire   try_y422 /* synthesis keep */; 
assign try_y422 = pix_data_in_422  ; 

Any ideas? The file is a part of the project/compilation - I checked this in the "Files" Tab in the Project Navigation section ... I also have open the file from there and saw the above lines present in the code.

Also added this - nothing helps:

(* preserve *) reg pix_data_in_422_db; 
always @(posedge pixclk_in) begin 
 pix_data_in_422_db <= pix_data_in_422;
end

Any ideas for the next steps?

I'm using Quartus Pro v19.3.0 build 200.

No, I cannot move to the latest Quartus version because the current project with its IPs is built basing on the mentioned version.

Actually the pix_data_in_422 signal doesn't drive any logic...

But is there a way it will not be optimized out and be able to be added to SignalTap ? None of the synthesis directives or attributes were able to prevent it from being optimized out...

yes, please see my previous answers