ContributorWell, there's your problem. It's getting optimized away. Tap the "upstream" signals that drive this or add virtual pin assignments to the signal in the Assignment Editor.
Super ContributorHi Dmitry,
Since you saying rtl viewer also cant be seen. Can you try to add some attribute e.g no prune (prevent from removed) and take a look at rtl viewer and stp if the wire can be traced
ContributorThis is like a black magic!
I've added the "noprune" attribute to the problematic signal and also the "keep" attribute to another signal, which is driven by the problematic signal - nothing helps.... No one of them is visible neither in RTL Viewer nor in SignalTap .
Here is how I added the attributes:
logic [PIX_DATA_BW-1:0] pix_data_in_422 /* synthesis noprune */; wire try_y422 /* synthesis keep */; assign try_y422 = pix_data_in_422 ;
Any ideas? The file is a part of the project/compilation - I checked this in the "Files" Tab in the Project Navigation section ... I also have open the file from there and saw the above lines present in the code.
Also added this - nothing helps:
(* preserve *) reg pix_data_in_422_db; always @(posedge pixclk_in) begin pix_data_in_422_db <= pix_data_in_422; end
Any ideas for the next steps?
