Signal output cannot be synthesized, bad synchronous description.

Are you making a counter with synchronous reset? An possible code is:

process(rst, clk_plstr)

begin

if(rst='1') then

count_reg <= ( others => '0' );

elsif(clk_plstr'event and clk_plstr='1') then

count_reg<=count_next;

end if;

end process;

count_next <= ( others =>'0' ) when (plsrep='1') else

count_reg+1;

Do you need to generate plsrep too?

Hi bretulus,

I had used the same logic to do this task.

I dont need to generate plsrep but i need to output my clock pulse (clk_plstr in my code) until the counting reach to some value(pls in my code).

The coding that I did for this is following:

process(clk_plstr,plsrep) ---to reset counter

begin

if rising_edge(plsrep)then

count_reg<= B"000000000000" ;

elsif(clk_plstr'event and clk_plstr='1')then

count_reg<=count_next;

end if;

if(clk_plstr'event and clk_plstr = '1')then

if(count_reg<=pls )then

output<='0';

else

output<='1';

end if;

else

output<='0';

end if;

end process;

count_next <=count_reg+'1' when(count_reg=B"000000000000" and plsrep='1') else

count_reg when (count_reg=B"000000000000") else

count_reg+'1' when (count_reg<pls)else

B"000000000000";

fout<=output; -----output the clock clk_plstr

This gives me the same error as:

"Signal output cannot be synthesized, bad synchronous description. The description style you are using to describe a synchronous element (register, memory, etc.) is not supported in the current software release."

I am not sure how I can perform this task.

Thank you very much.

There are some lines in your that may cause problems:

if rising_edge(plsrep)then

count_reg<= B"000000000000" ;

elsif(clk_plstr'event and clk_plstr='1')then

count_reg<=count_next;

end if;

The rising_edge means that plsrep is used as a clock signal. In a synchronous system ( fpgas ) you have only one clock. You may try:

if plsrep = '1' then

count_reg<= B"000000000000" ;

elsif(clk_plstr'event and clk_plstr='1')then

count_reg<=count_next;

end if;

But plsrep in this code works like an asynchronous reset. So don't use reset in the register declaration:

process(clk_plstr)

begin

if(clk_plstr'event and clk_plstr='1') then

count_reg<=count_next;

end if;

end process;

count_next <=count_reg+'1' when(count_reg=B"000000000000" and plsrep='1') else

count_reg when (count_reg=B"000000000000") else

count_reg+'1' when (count_reg<pls)else

B"000000000000";

Hi,

I need to generate clk_plstr.

Hi bretelus ,

Thank you for the sugesstion.It works if I used plsrep='1'.

But when I try to output the clock pulse(clk_plstr here) then I again get the same error as:

"Signal output cannot be synthesized, bad synchronous description. The description style you are using to describe a synchronous element (register, memory, etc.) is not supported in the current software release."

The code to output this clock pluse looks like following:

process(clk_plstr)

begin

..........

if(clk_plstr'event and clk_plstr = '1')then ----xst error to output like this?

if(count_reg<=pls )then

output<='1';

else

output<='0';

end if;

end process;

It would be very helpful if you could point out the problem that I am getting now.Thank you

For a start, XST is a Xilinx tool - this is an Altera forum (Xilinx's competitor).

Anyway, the error cant be seen in the code you have posted, post the whole code.

Hi Tricky,

I right now I am doing simulation only.So I was trying both software quartus and xilinx.

Following is the code which I think is giving me this error:

process(clk_plstr)

begin

if(clk_plstr'event and clk_plstr='1') then

count_reg<=count_next;

if(count_reg<=pls )then

output<='1';

else

output<='0';

end if;

end if;

end process;

count_next <=count_reg+'1' when(count_reg=B"000" and plsrep='1') else

count_reg when (count_reg=B"000") else

count_reg+'1' when (count_reg<pls)else

B"000";

fout<=output;

Thank you