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Altera_Forum
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12 years ago

Signal output cannot be synthesized, bad synchronous description.

Hi , I have been using vhdl programming for my project and I am trying to make a counter to count clock signal(clk_plstr),the counter is reset with another pulse signal(plsrep in my code). I...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
12 years ago

Hi Tricky,

I right now I am doing simulation only.So I was trying both software quartus and xilinx.

Following is the code which I think is giving me this error:

process(clk_plstr)

begin

if(clk_plstr'event and clk_plstr='1') then

count_reg<=count_next;

if(count_reg<=pls )then

output<='1';

else

output<='0';

end if;

end if;

end process;

count_next <=count_reg+'1' when(count_reg=B"000" and plsrep='1') else

count_reg when (count_reg=B"000") else

count_reg+'1' when (count_reg<pls)else

B"000";

fout<=output;

Thank you