Signal output cannot be synthesized, bad synchronous description.

There are some lines in your that may cause problems:

if rising_edge(plsrep)then

count_reg<= B"000000000000" ;

elsif(clk_plstr'event and clk_plstr='1')then

count_reg<=count_next;

end if;

The rising_edge means that plsrep is used as a clock signal. In a synchronous system ( fpgas ) you have only one clock. You may try:

if plsrep = '1' then

count_reg<= B"000000000000" ;

elsif(clk_plstr'event and clk_plstr='1')then

count_reg<=count_next;

end if;

But plsrep in this code works like an asynchronous reset. So don't use reset in the register declaration:

process(clk_plstr)

begin

if(clk_plstr'event and clk_plstr='1') then

count_reg<=count_next;

end if;

end process;

count_next <=count_reg+'1' when(count_reg=B"000000000000" and plsrep='1') else

count_reg when (count_reg=B"000000000000") else

count_reg+'1' when (count_reg<pls)else

B"000000000000";