Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
12 years ago

Signal output cannot be synthesized, bad synchronous description.

Hi , I have been using vhdl programming for my project and I am trying to make a counter to count clock signal(clk_plstr),the counter is reset with another pulse signal(plsrep in my code). I...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
12 years ago

For a start, XST is a Xilinx tool - this is an Altera forum (Xilinx's competitor).

Anyway, the error cant be seen in the code you have posted, post the whole code.