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Altera_Forum's avatar
Altera_Forum
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12 years ago

Signal output cannot be synthesized, bad synchronous description.

Hi , I have been using vhdl programming for my project and I am trying to make a counter to count clock signal(clk_plstr),the counter is reset with another pulse signal(plsrep in my code). I...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
12 years ago

According to the codes you and me posted, clk_plstr should be the general clock of the system, so you don't need to generate it. You use it. But if you're trying to slow down the general clock you have to use a clock enable scheme. Give more details of your design.