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Altera_Forum's avatar
Altera_Forum
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12 years ago

Signal output cannot be synthesized, bad synchronous description.

Hi , I have been using vhdl programming for my project and I am trying to make a counter to count clock signal(clk_plstr),the counter is reset with another pulse signal(plsrep in my code). I...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
12 years ago

Are you making a counter with synchronous reset? An possible code is:

process(rst, clk_plstr)

begin

if(rst='1') then

count_reg <= ( others => '0' );

elsif(clk_plstr'event and clk_plstr='1') then

count_reg<=count_next;

end if;

end process;

count_next <= ( others =>'0' ) when (plsrep='1') else

count_reg+1;

Do you need to generate plsrep too?