Altera_Forum
Honored Contributor
8 years ago[SDC] Input/Output delay for All ports -> script writing
Hi All,
How can I create the timing constraints (set_input/output_delay) for all ports (excepting clocks and reset ports)? Let's say the design has the following clocks: clk0, clk1, clk2 and following resets: rstn0, rstn1, rstn2 and hundreds of other ports. How can I write a script, which set input delays of 0ns for all input ports (excepting clk0, clk1, clk2, rstn0, rstn1, rstn2) and output delays of 0ns for all output ports? Thank you!