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Altera_Forum
Honored Contributor
Honored Contributor[SDC] Input/Output delay for All ports -> script writing
Hi All, How can I create the timing constraints (set_input/output_delay) for all ports (excepting clocks and reset ports)? Let's say the design has the following clocks: clk0, clk1, clk2 ...
Altera_ForumHonored Contributor
Honored ContributorDoes the [get_ports out*] list all the output ports and [get_ports in*] list all the input ports?
How can I exclude certain ports from these listings? Is it possible to work with collections here? How to remove the input/output delay constraints from the certain ports? Thank you!
