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Altera_Forum
Honored Contributor
8 years ago[SDC] Input/Output delay for All ports -> script writing
Hi All, How can I create the timing constraints (set_input/output_delay) for all ports (excepting clocks and reset ports)? Let's say the design has the following clocks: clk0, clk1, clk2 ...
Altera_Forum
Honored Contributor
8 years agorunning the all_inputs command gives the same result:
Error:ERROR: Quartus Prime Tcl command "all_inputs" is only available for use in the following executables:
Error: quartus_fit
Error: quartus_sta
Error: while executing
Error:"all_inputs" So, what's the solution?