Forum Discussion
Altera_Forum
Honored Contributor
8 years agoI don't quite understand what you want to accomplish here. Your input and output delays could be 0 for a *minimum* delay, but you also need a matching *maximum* delay. The range of delay is required to give the Fitter an idea of what it has to work with as to the placement of the input or output register.
set_input_delay -clock <virtual clock that drives upstream device> -max [get_ports in*] <max external delay based on tco of upstream device and board delays> set_input_delay -clock <virtual clock that drives upstream device> -min [get_ports in*] 0 set_output_delay -clock <virtual clock that drives downstream device> -max [get_ports out*] <max external delay based on tsu of downstream device and board delays> set_output_delay -clock <virtual clock that drives downstream device> -min [get_ports out*] 0