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Honored Contributor
Honored Contributor[SDC] Input/Output delay for All ports -> script writing
Hi All, How can I create the timing constraints (set_input/output_delay) for all ports (excepting clocks and reset ports)? Let's say the design has the following clocks: clk0, clk1, clk2 ...
Altera_ForumHonored Contributor
Honored ContributorI don't quite understand what you want to accomplish here. Your input and output delays could be 0 for a *minimum* delay, but you also need a matching *maximum* delay. The range of delay is required to give the Fitter an idea of what it has to work with as to the placement of the input or output register.
set_input_delay -clock <virtual clock that drives upstream device> -max [get_ports in*] <max external delay based on tco of upstream device and board delays> set_input_delay -clock <virtual clock that drives upstream device> -min [get_ports in*] 0 set_output_delay -clock <virtual clock that drives downstream device> -max [get_ports out*] <max external delay based on tsu of downstream device and board delays> set_output_delay -clock <virtual clock that drives downstream device> -min [get_ports out*] 0
