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Altera_Forum
Honored Contributor
Honored Contributor[SDC] Input/Output delay for All ports -> script writing
Hi All, How can I create the timing constraints (set_input/output_delay) for all ports (excepting clocks and reset ports)? Let's say the design has the following clocks: clk0, clk1, clk2 ...
Altera_ForumHonored Contributor
Honored Contributorthis is exactly what I asked for :-) how to list ALL input ports without listing each port separately!
How can I make a collection (list) of ALL the input ports (something like 'create_collection all_inputs')?
