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Honored Contributor
Honored Contributor[SDC] Input/Output delay for All ports -> script writing
Hi All, How can I create the timing constraints (set_input/output_delay) for all ports (excepting clocks and reset ports)? Let's say the design has the following clocks: clk0, clk1, clk2 ...
Altera_ForumHonored Contributor
Honored ContributorIt's very simple - just several lines...
set_time_format -unit ns -decimal_places 3
create_clock -name {clk} -period 10.000 -waveform { 0.000 5.000 }
create_clock -name {fifo_rclk} -period 10.000 -waveform { 0.000 5.000 }
set_input_delay -clock { clk } 5
set_output_delay -clock { clk } 5 
