SDC - What clock should the input pin be relative to?

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Hello,

signal_x in an input pin to my FPGA.

signal_x is synchronous to clock_x which is also an input pin.

clock_x drives a pll input and becomes pll_clock_x.

pll_clock_x is phase aligned to clock_x and is used to latch signal_x.

Besides feeding the PLL - clock_x isn't used anywhere else in the design.

Question:

When constraining signal_x for input_delay - what clock should be used? clock_x or pll_clock_x ?

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In theory TQ allows any clock to be used as reference as long as it is known to it and you know the right figures relative to the clock! but naturally you will use the clock input at the pin (clock_x) as you know the data/clock offsets (for set_input_delay)

Well,

This is exactly what I thought...and did.

I.E: set_input_delay relative to the clock pin (not the Pll output).

But then I started getting setup timing violations on the nets latched by pll_clock_x.

The input delay I set wasn't strict, the design isn't congested and the frequency of clock_x is 40Mhz.

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Well,

This is exactly what I thought...and did.

I.E: set_input_delay relative to the clock pin (not the Pll output).

But then I started getting setup timing violations on the nets latched by pll_clock_x.

The input delay I set wasn't strict, the design isn't congested and the frequency of clock_x is 40Mhz.

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I take it that io setup/hold are ok but internally setup fails and does so on 40MHz. This is unusual in most devices. You may have some other issues.

you need to describe more details about your design clocking and failed paths.

"IN_PCLOCK_RX_12B" under the Launch Clock tab is my "clock_x" pin.

The very long name under the Latch Clock tab is my "clock_x_pll"

Any of the names under the From Node is my "signal_x".

Any of the names under the To Node represent the "clock_x_pll" registered version of "signal_x".

This means io paths are failing. what are your set input delay figures.

What is the figure for setup relationship on those paths.

Have you added derive_pll_clocks. what mode is the pll. you may try remove pll

It's an integer PLL

The set_input_delay min is 0.1ns

The set_input_delay max is 10ns

The period is 25ns (40Mhz).

Regarding the "derive_pll_clocks" command - yes. I used it and requested it to create the base clocks.

So I didn't have to manually use neither create_clock nor create_generated_clock - all have been done automatically by the tool via the derive_pll_clocks command.

do you mean you haven't declared the base clock of 40MHz? you need that even though PLL is connected to it.

Look at the failedpath table: what is the figure for setup relationship.This should be 25ns.

your set input delay of.1/10 means early margin is very close to edge. Is that how your external chip and board delay wants?

is your pll in normal mode or any other mode?

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do you mean you haven't declared the base clock of 40MHz?

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Sorry. This I did of course.

The PLL is set to normal mode.

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your set input delay of.1/10 means early margin is very close to edge.

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The data signals are jittery so this is why I set the max delay to 10. But even at 10ns - it leaves 15ns which I think is enough for the tool to do a good job.

I'll rerun TQ and check for the relationship.

OK, I'll try that.

Should I change something in the SDC file after doing so ?

Just looked again. The PLL is configured as "normal"