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Altera_Forum
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9 years ago

SDC - What clock should the input pin be relative to?

Hello, signal_x in an input pin to my FPGA. signal_x is synchronous to clock_x which is also an input pin. clock_x drives a pll input and becomes pll_clock_x. pll_clock_x is pha...
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Altera_Forum
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9 years ago

yes 15 ns is plenty of margin. You might better set pll to source synchronous mode. That way the clock data offset at pins is retained by pll