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Altera_Forum
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9 years ago

SDC - What clock should the input pin be relative to?

Hello, signal_x in an input pin to my FPGA. signal_x is synchronous to clock_x which is also an input pin. clock_x drives a pll input and becomes pll_clock_x. pll_clock_x is pha...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
9 years ago

Well,

This is exactly what I thought...and did.

I.E: set_input_delay relative to the clock pin (not the Pll output).

But then I started getting setup timing violations on the nets latched by pll_clock_x.

The input delay I set wasn't strict, the design isn't congested and the frequency of clock_x is 40Mhz.