Forum Discussion
Altera_Forum
Honored Contributor
Honored ContributorSDC - What clock should the input pin be relative to?
Hello, signal_x in an input pin to my FPGA. signal_x is synchronous to clock_x which is also an input pin. clock_x drives a pll input and becomes pll_clock_x. pll_clock_x is pha...
Altera_ForumHonored Contributor
Honored ContributorWell,
This is exactly what I thought...and did. I.E: set_input_delay relative to the clock pin (not the Pll output). But then I started getting setup timing violations on the nets latched by pll_clock_x. The input delay I set wasn't strict, the design isn't congested and the frequency of clock_x is 40Mhz.
