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Altera_Forum
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9 years ago

SDC - What clock should the input pin be relative to?

Hello, signal_x in an input pin to my FPGA. signal_x is synchronous to clock_x which is also an input pin. clock_x drives a pll input and becomes pll_clock_x. pll_clock_x is pha...
Altera_Forum's avatar
Altera_Forum
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9 years ago

do you mean you haven't declared the base clock of 40MHz? you need that even though PLL is connected to it.

Look at the failedpath table: what is the figure for setup relationship.This should be 25ns.

your set input delay of.1/10 means early margin is very close to edge. Is that how your external chip and board delay wants?

is your pll in normal mode or any other mode?