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Altera_Forum
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9 years ago

SDC - What clock should the input pin be relative to?

Hello, signal_x in an input pin to my FPGA. signal_x is synchronous to clock_x which is also an input pin. clock_x drives a pll input and becomes pll_clock_x. pll_clock_x is pha...
Altera_Forum's avatar
Altera_Forum
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9 years ago

It's an integer PLL

The set_input_delay min is 0.1ns

The set_input_delay max is 10ns

The period is 25ns (40Mhz).

Regarding the "derive_pll_clocks" command - yes. I used it and requested it to create the base clocks.

So I didn't have to manually use neither create_clock nor create_generated_clock - all have been done automatically by the tool via the derive_pll_clocks command.