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Altera_Forum
Honored Contributor
Honored ContributorSDC - What clock should the input pin be relative to?
Hello, signal_x in an input pin to my FPGA. signal_x is synchronous to clock_x which is also an input pin. clock_x drives a pll input and becomes pll_clock_x. pll_clock_x is pha...
Altera_ForumHonored Contributor
Honored ContributorOK, I'll try that.
Should I change something in the SDC file after doing so ? Just looked again. The PLL is configured as "normal"
