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Hello,
signal_x in an input pin to my FPGA.
signal_x is synchronous to clock_x which is also an input pin.
clock_x drives a pll input and becomes pll_clock_x.
pll_clock_x is phase aligned to clock_x and is used to latch signal_x.
Besides feeding the PLL - clock_x isn't used anywhere else in the design.
Question:
When constraining signal_x for input_delay - what clock should be used? clock_x or pll_clock_x ?
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In theory TQ allows any clock to be used as reference as long as it is known to it and you know the right figures relative to the clock! but naturally you will use the clock input at the pin (clock_x) as you know the data/clock offsets (for set_input_delay)
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