Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
9 years ago

SDC - What clock should the input pin be relative to?

Hello, signal_x in an input pin to my FPGA. signal_x is synchronous to clock_x which is also an input pin. clock_x drives a pll input and becomes pll_clock_x. pll_clock_x is pha...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
9 years ago

"IN_PCLOCK_RX_12B" under the Launch Clock tab is my "clock_x" pin.

The very long name under the Latch Clock tab is my "clock_x_pll"

Any of the names under the From Node is my "signal_x".

Any of the names under the To Node represent the "clock_x_pll" registered version of "signal_x".