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Altera_Forum
Honored Contributor
Honored ContributorSDC - What clock should the input pin be relative to?
Hello, signal_x in an input pin to my FPGA. signal_x is synchronous to clock_x which is also an input pin. clock_x drives a pll input and becomes pll_clock_x. pll_clock_x is pha...
Altera_ForumHonored Contributor
Honored Contributor --- Quote Start --- do you mean you haven't declared the base clock of 40MHz? --- Quote End --- Sorry. This I did of course. The PLL is set to normal mode. --- Quote Start --- your set input delay of.1/10 means early margin is very close to edge. --- Quote End --- The data signals are jittery so this is why I set the max delay to 10. But even at 10ns - it leaves 15ns which I think is enough for the tool to do a good job. I'll rerun TQ and check for the relationship.
