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Altera_Forum
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9 years ago

SDC - What clock should the input pin be relative to?

Hello, signal_x in an input pin to my FPGA. signal_x is synchronous to clock_x which is also an input pin. clock_x drives a pll input and becomes pll_clock_x. pll_clock_x is pha...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
9 years ago

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do you mean you haven't declared the base clock of 40MHz?

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Sorry. This I did of course.

The PLL is set to normal mode.

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your set input delay of.1/10 means early margin is very close to edge.

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The data signals are jittery so this is why I set the max delay to 10. But even at 10ns - it leaves 15ns which I think is enough for the tool to do a good job.

I'll rerun TQ and check for the relationship.