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Altera_Forum's avatar
Altera_Forum
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15 years ago

Modelsim - VHDL common question.

Dear all my friend

I make this thread to post the question related to Modelsim and VHDL

I hope everybody can help me answer.

Thank you very much.

Best regards.

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  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    Dear Kaz

    Why I can not use port map inside of If command?

    Could you check this code for me?

    In this code, I use a component multvhdl to multiply A0 and X0. When I push the port map, Quartus alway say the error at port map.

    Thanks Kaz very much. 

    LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_signed.all;
USE IEEE.numeric_std.all;
ENTITY STEP IS
port(CLK, CLK_40n  :IN  STD_LOGIC;
	X0	:IN STD_LOGIC_VECTOR(15 downto 0);
	Yn	:BUFFER STD_LOGIC_VECTOR(15 downto 0));
END STEP;
ARCHITECTURE STEP_arch OF STEP IS
Component Multvhdl
Port (
	A,B				 	: In Signed(15 downto 0); --A*B
	Result_out			: Out Signed(31 downto 0);
	CLK					: In std_logic);
end component;
SIGNAL A0,A1,A2,A3,A4	:STD_LOGIC_VECTOR(15 downto 0);
SIGNAL B1,B2,B3,B4		:STD_LOGIC_VECTOR(15 downto 0);
SIGNAL Y4,Y3,Y2,Y1		:STD_LOGIC_VECTOR(15 downto 0);
SIGNAL X1,X2,X3,X4		:STD_LOGIC_VECTOR(15 downto 0);
--SIGNAL mula,mulb		:STD_LOGIC_VECTOR(15 downto 0);
--SIGNAL mulr				:STD_LOGIC_VECTOR(31 downto 0);
SIGNAL adda,addb,addr	:STD_LOGIC_VECTOR(31 downto 0);
SIGNAL CNT				:STD_LOGIC_VECTOR(4 downto 0);
BEGIN
A0  <= "0000000000000011";--3  
A1  <=  std_logic_vector(to_signed(16#000B#,16));--11      
A2  <=  std_logic_vector(to_signed(16#0011#,16));--17    
A3  <=  std_logic_vector(to_signed(16#000B#,16));--11
A4  <=  std_logic_vector(to_signed(16#0003#,16));--3  
B1  <=  std_logic_vector(to_signed(16#5D3F#,16));--23871   
B2  <=  std_logic_vector(to_signed(16#9A14#,16));-- -26092
B3  <=  std_logic_vector(to_signed(16#3181#,16));--12637
B4  <=  std_logic_vector(to_signed(16#F6FF#,16));-- -2305
 
GEN:block
BEGIN
PROCESS(CLK_40n,CLK)
BEGIN
IF CLK_40n'EVENT and CLK_40n='1' THEN
	CNT <=CNT+1;
IF CNT="00000" THEN
M0: Multvhdl port map (A0,X0,adda,CLK);
ELSIF CNT="00001" THEN
	addb <=  A1*X1;
ELSIF CNT="00010" THEN
	adda <=  adda+addb;
	addb <=  A2*X2;
ELSIF CNT="00011" THEN
	adda <=  adda+addb;
	addb <=  a3*x3;
ELSIF CNT="00100" THEN
	adda <=  adda+addb;
	addb <=  a4*x4;		
ELSIF CNT="00101" THEN
	adda <=  adda+addb;
	addb <=  B1*Y1;
ELSIF CNT="00110" THEN
	adda <=  adda+addb;
	addb <=  B2*Y2;
ELSIF CNT="00111" THEN
	adda <=  adda+addb;
	addb <=  B3*Y3;
ELSIF CNT="01000" THEN
	adda <=  adda+addb;
	addb <=  B4*Y4;
ELSIF CNT="01001" THEN
	Yn <=   adda(15 downto 0)+addb(15 downto 0);
ELSIF CNT="01010" THEN
	Y1       <=  Yn;
	Y2       <=  Y1;
	Y3       <=  Y2;
	Y4       <=  Y3;
	X4       <=  X3;
	X3       <=  X2;
	X2       <=  X1;
	X1       <=  X0;
	CNT     <=  "00000";
END IF;
END IF;
END PROCESS;
END BLOCK GEN;
END STEP_arch;

    When I push port map outside IF command, it's ok. But I can not do that for this code.
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    15 years ago

    You are not allowed to instantiate on "if".

    The only conditional instantiation allowed is through generate but never mind.

    Instantiate your component outside process then set if on the signal connected to its output.
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    15 years ago

    you cannot instantiate entities on the fly - they always exist. You need clock enables (or a data valid signal) to notify when to use a component.

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    15 years ago

    Dear Kaz and Tricky

    Could you tell more about method connect to my component from IF command? I'm very new with VHDL therefore I don't know that method.

    Thank Kaz and Tricky very much.
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    15 years ago

    I cannot connect a component inside an if command inside a process, you can only do it inside a generate. but this means you either include it in the FPGA or not, it does not change when the design is running.

    and example: 

    
mult_gen : if INCLUDE_MULT = true generate
  M0: Multvhdl port map (A0,X0,adda,CLK);
end generate mult_gen;

    INCLUDE_MULT must be a constant or a generic. Either way, the multipler is NOT generated while the design is running.
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    15 years ago

    --- Quote Start ---

    I cannot connect a component inside an if command inside a process, you can only do it inside a generate. but this means you either include it in the FPGA or not, it does not change when the design is running.

    and example: 

    
mult_gen : if INCLUDE_MULT = true generate
  M0: Multvhdl port map (A0,X0,adda,CLK);
end generate mult_gen;

    INCLUDE_MULT must be a constant or a generic. Either way, the multipler is NOT generated while the design is running.

    --- Quote End ---

    Thank Tricky very much.

    I try it now.
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    15 years ago

    Dear my friends

    Thank you very much for your help.

    Now, I still have a big issue with modelsim. When I run my code with Quartus => it's ok. But when i simulate with modelsim there were a lot of wanning and I didn't see any result. I had initialed all of signal but it still has error.

    Could you help me?

    This is wanning:

    --- Quote Start ---

    # ** Error: Value of lpm_representation parameter must be SIGNED or UNSIGNED!# Time: 0 ns Iteration: 0 Instance: /testbench_step/u/adder1# ** Error: Illegal lpm_representation property value for LPM_MULT!# Time: 0 ns Iteration: 0 Instance: /testbench_step/u/mull# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).# Time: 0 ns Iteration: 0 Instance: /testbench_step/u/mull# ** Error: Illegal lpm_representation property value for LPM_MULT!# Time: 0 ns Iteration: 1 Instance: /testbench_step/u/mull# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).# Time: 0 ns Iteration: 1 Instance: /testbench_step/u/mull# ** Error: Illegal lpm_representation property value for LPM_MULT!# Time: 40 ns Iteration: 3 Instance: /testbench_step/u/mull# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).# Time: 40 ns Iteration: 3 Instance: /testbench_step/u/mull

    --- Quote End ---

    This is my code: 

    
LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
--Use IEEE.numeric_std.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_signed.all;
LIBRARY lpm;
USE lpm.LPM_COMPONENTS.ALL;
ENTITY STEP IS
port(CLK, CLK_40n  :IN  STD_LOGIC:='0';
 X0 :IN STD_LOGIC_VECTOR(15 downto 0):="0000000000000000";
 Yn :BUFFER STD_LOGIC_VECTOR(15 downto 0):="0000000000000000");
END STEP;
ARCHITECTURE STEP_arch OF STEP IS
SIGNAL A0,A1,A2,B1,B2 :STD_LOGIC_VECTOR(15 downto 0):=(others=>'0');
SIGNAL Y2,Y1,X1,X2  :STD_LOGIC_VECTOR(15 downto 0):=(others=>'0');
SIGNAL mula,mulb  :STD_LOGIC_VECTOR(15 downto 0):=(others=>'0');
SIGNAL mulr    :STD_LOGIC_VECTOR(31 downto 0):=(others=>'0');
SIGNAL adda,addb,addr :STD_LOGIC_VECTOR(15 downto 0):=(others=>'0');
SIGNAL CNT    :STD_LOGIC_VECTOR(4 downto 0):=(others=>'0');
BEGIN
mull: lpm_mult
generic map(LPM_WIDTHA=>16,LPM_WIDTHB=>16,LPM_WIDTHS=>16,LPM_WIDTHP=>32,LPM_REPRESENTATION=>"signed",LPM_PIPELINE=>1)
port map(dataa=> mula,datab=> mulb,clock=> clk,result=> mulr);
adder1: lpm_add_sub
generic map(lpm_width=>16,LPM_REPRESENTATION=>"signed",lpm_pipeline=>1)
port map(dataa=>adda,datab=>addb,clock=> clk,result=>addr);
--Q15
A0  <=  "0000000000101010";--42      (0.00128)
A1  <=  "0000000001010000";--80      (0.00244)
A2  <=  "0000000000101010";--42      (0.00128)
B1  <=  "0111100101001000";--31048   (0.94754)
B2  <=  "1100011000010100";---14828  (-0.4525)
GEN:block
BEGIN
PROCESS(CLK_40n)
BEGIN
IF CLK_40n'EVENT and CLK_40n='1' THEN
 CNT <=CNT+"00001";
IF CNT="00000" THEN
 mula <=  A0;
 mulb <=  X0; 
ELSIF CNT="00010" THEN
 adda <=  mulr(30 downto 15);
 mula <=  A1;
 mulb <=  X1;
ELSIF CNT="00100" THEN
 addb <=  mulr(30 downto 15);
 mula <=  A2;
 mulb <=  X2;
ELSIF CNT="00110" THEN
 adda <=  addr;
 addb <=  mulr(30 downto 15);
 mula <=  B1;
 mulb <=  Y1;
ELSIF CNT="01000" THEN
 adda <=   addr;
 addb <=   mulr(30 downto 15);
 mula <=   B2;
 mulb <=   Y2;
ELSIF CNT="01010" THEN
 adda <=   addr;
 addb <=   mulr(30 downto 15);
ELSIF CNT="01100" THEN
 Yn <=   (addr(15) & addr(13 downto 0) & '0');
-- Yn1<=addr;
-- Yn2<=addr(14 downto 0) &'0'; -- the same with Yn
ELSIF CNT="01110" THEN
 Y1       <=  Yn;
 Y2       <=  Y1;
 X2       <=  X1;
 X1       <=  X0;
 CNT     <=  "00000";
END IF;
END IF;
END PROCESS;
END BLOCK GEN;
END STEP_arch;

    This is my testbench 

    
LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_signed.all;
ENTITY Testbench_STEP IS
END Testbench_STEP;
ARCHITECTURE testbench_STEP_arch OF Testbench_STEP IS
component step
port(
 CLK, CLK_40n  :IN  STD_LOGIC:='0';
 X0 :IN STD_LOGIC_VECTOR(15 downto 0):=(others=>'0');
 Yn :BUFFER STD_LOGIC_VECTOR(15 downto 0):=(others=>'0')
 );
end component;
 
SIGNAL CLK, CLK_40n   : STD_LOGIC:='0';
SIGNAL X0    : STD_LOGIC_VECTOR(15 downto 0):=(others=>'0');
SIGNAL Yn    : STD_LOGIC_VECTOR(15 downto 0):=(others=>'0');
BEGIN
 
U: step port map (
  CLK  => CLK, 
  CLK_40n => CLK_40n,
  X0   =>  X0,
  Yn  =>  Yn
  );
 
tb: PROCESS
BEGIN
X0<= "0100000000000000";
loop
clk_40n <= '0' ; wait for 40 ns;
clk_40n <= '1' ; wait for 40 ns;
end loop;
END PROCESS;
END testbench_STEP_arch;
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    15 years ago

    --- Quote Start ---

    changed "signed" to "SIGNED"

    --- Quote End ---

    Thank Tricky.

    I done it. The result is ok, But it still has a little error at the biginning, when time is 0 ns. Could you check it for me. thanks

    This is error

    --- Quote Start ---

    # ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).# Time: 0 ns Iteration: 0 Instance: /testbench_step/u/adder1/l2/v# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).# Time: 0 ns Iteration: 0 Instance: /testbench_step/u/adder1/l2/v# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).# Time: 0 ns Iteration: 0 Instance: /testbench_step/u/adder1/l2/v# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).# Time: 0 ns Iteration: 0 Instance: /testbench_step/u/mull# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).# Time: 0 ns Iteration: 0 Instance: /testbench_step/u/mull# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).# Time: 0 ns Iteration: 0 Instance: /testbench_step/u/mull

    --- Quote End ---

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    15 years ago

    Looks like its internal to the adder and multipler, nothing you can do about it.

    You can turn off these warnings in modelsim by going to Simulate -> Runtime Options -> tick "Ignore warnings from numeric_std and synopsys packages"