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Altera_Forum
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15 years ago

Modelsim - VHDL common question.

Dear all my friend I make this thread to post the question related to Modelsim and VHDL I hope everybody can help me answer. Thank you very much. Best regards.
Altera_Forum's avatar
Altera_Forum
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15 years ago

you cannot instantiate entities on the fly - they always exist. You need clock enables (or a data valid signal) to notify when to use a component.