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Altera_Forum
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15 years ago

Modelsim - VHDL common question.

Dear all my friend I make this thread to post the question related to Modelsim and VHDL I hope everybody can help me answer. Thank you very much. Best regards.
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

You are not allowed to instantiate on "if".

The only conditional instantiation allowed is through generate but never mind.

Instantiate your component outside process then set if on the signal connected to its output.