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I cannot connect a component inside an if command inside a process, you can only do it inside a generate. but this means you either include it in the FPGA or not, it does not change when the design is running.
and example:
mult_gen : if INCLUDE_MULT = true generate
M0: Multvhdl port map (A0,X0,adda,CLK);
end generate mult_gen;
INCLUDE_MULT must be a constant or a generic. Either way, the multipler is NOT generated while the design is running.
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Thank Tricky very much.
I try it now.
Honored Contributor
