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Altera_Forum
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15 years ago

Modelsim - VHDL common question.

Dear all my friend I make this thread to post the question related to Modelsim and VHDL I hope everybody can help me answer. Thank you very much. Best regards.
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

I cannot connect a component inside an if command inside a process, you can only do it inside a generate. but this means you either include it in the FPGA or not, it does not change when the design is running.

and example: 


mult_gen : if INCLUDE_MULT = true generate
  M0: Multvhdl port map (A0,X0,adda,CLK);
end generate mult_gen;

INCLUDE_MULT must be a constant or a generic. Either way, the multipler is NOT generated while the design is running.