Modelsim - VHDL common question.

Dear Kaz

Why I can not use port map inside of If command?

Could you check this code for me?

In this code, I use a component multvhdl to multiply A0 and X0. When I push the port map, Quartus alway say the error at port map.

Thanks Kaz very much.

LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_signed.all;
USE IEEE.numeric_std.all;
ENTITY STEP IS
port(CLK, CLK_40n  :IN  STD_LOGIC;
	X0	:IN STD_LOGIC_VECTOR(15 downto 0);
	Yn	:BUFFER STD_LOGIC_VECTOR(15 downto 0));
END STEP;
ARCHITECTURE STEP_arch OF STEP IS
Component Multvhdl
Port (
	A,B				 	: In Signed(15 downto 0); --A*B
	Result_out			: Out Signed(31 downto 0);
	CLK					: In std_logic);
end component;
SIGNAL A0,A1,A2,A3,A4	:STD_LOGIC_VECTOR(15 downto 0);
SIGNAL B1,B2,B3,B4		:STD_LOGIC_VECTOR(15 downto 0);
SIGNAL Y4,Y3,Y2,Y1		:STD_LOGIC_VECTOR(15 downto 0);
SIGNAL X1,X2,X3,X4		:STD_LOGIC_VECTOR(15 downto 0);
--SIGNAL mula,mulb		:STD_LOGIC_VECTOR(15 downto 0);
--SIGNAL mulr				:STD_LOGIC_VECTOR(31 downto 0);
SIGNAL adda,addb,addr	:STD_LOGIC_VECTOR(31 downto 0);
SIGNAL CNT				:STD_LOGIC_VECTOR(4 downto 0);
BEGIN
A0  <= "0000000000000011";--3  
A1  <=  std_logic_vector(to_signed(16#000B#,16));--11      
A2  <=  std_logic_vector(to_signed(16#0011#,16));--17    
A3  <=  std_logic_vector(to_signed(16#000B#,16));--11
A4  <=  std_logic_vector(to_signed(16#0003#,16));--3  
B1  <=  std_logic_vector(to_signed(16#5D3F#,16));--23871   
B2  <=  std_logic_vector(to_signed(16#9A14#,16));-- -26092
B3  <=  std_logic_vector(to_signed(16#3181#,16));--12637
B4  <=  std_logic_vector(to_signed(16#F6FF#,16));-- -2305
 
GEN:block
BEGIN
PROCESS(CLK_40n,CLK)
BEGIN
IF CLK_40n'EVENT and CLK_40n='1' THEN
	CNT <=CNT+1;
IF CNT="00000" THEN
M0: Multvhdl port map (A0,X0,adda,CLK);
ELSIF CNT="00001" THEN
	addb <=  A1*X1;
ELSIF CNT="00010" THEN
	adda <=  adda+addb;
	addb <=  A2*X2;
ELSIF CNT="00011" THEN
	adda <=  adda+addb;
	addb <=  a3*x3;
ELSIF CNT="00100" THEN
	adda <=  adda+addb;
	addb <=  a4*x4;		
ELSIF CNT="00101" THEN
	adda <=  adda+addb;
	addb <=  B1*Y1;
ELSIF CNT="00110" THEN
	adda <=  adda+addb;
	addb <=  B2*Y2;
ELSIF CNT="00111" THEN
	adda <=  adda+addb;
	addb <=  B3*Y3;
ELSIF CNT="01000" THEN
	adda <=  adda+addb;
	addb <=  B4*Y4;
ELSIF CNT="01001" THEN
	Yn <=   adda(15 downto 0)+addb(15 downto 0);
ELSIF CNT="01010" THEN
	Y1       <=  Yn;
	Y2       <=  Y1;
	Y3       <=  Y2;
	Y4       <=  Y3;
	X4       <=  X3;
	X3       <=  X2;
	X2       <=  X1;
	X1       <=  X0;
	CNT     <=  "00000";
END IF;
END IF;
END PROCESS;
END BLOCK GEN;
END STEP_arch;	

When I push port map outside IF command, it's ok. But I can not do that for this code.