Modelsim - VHDL common question.

Dear my friends

Thank you very much for your help.

Now, I still have a big issue with modelsim. When I run my code with Quartus => it's ok. But when i simulate with modelsim there were a lot of wanning and I didn't see any result. I had initialed all of signal but it still has error.

Could you help me?

This is wanning:

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# ** Error: Value of lpm_representation parameter must be SIGNED or UNSIGNED!# Time: 0 ns Iteration: 0 Instance: /testbench_step/u/adder1# ** Error: Illegal lpm_representation property value for LPM_MULT!# Time: 0 ns Iteration: 0 Instance: /testbench_step/u/mull# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).# Time: 0 ns Iteration: 0 Instance: /testbench_step/u/mull# ** Error: Illegal lpm_representation property value for LPM_MULT!# Time: 0 ns Iteration: 1 Instance: /testbench_step/u/mull# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).# Time: 0 ns Iteration: 1 Instance: /testbench_step/u/mull# ** Error: Illegal lpm_representation property value for LPM_MULT!# Time: 40 ns Iteration: 3 Instance: /testbench_step/u/mull# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).# Time: 40 ns Iteration: 3 Instance: /testbench_step/u/mull

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This is my code:

LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
--Use IEEE.numeric_std.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_signed.all;
LIBRARY lpm;
USE lpm.LPM_COMPONENTS.ALL;
ENTITY STEP IS
port(CLK, CLK_40n  :IN  STD_LOGIC:='0';
 X0 :IN STD_LOGIC_VECTOR(15 downto 0):="0000000000000000";
 Yn :BUFFER STD_LOGIC_VECTOR(15 downto 0):="0000000000000000");
END STEP;
ARCHITECTURE STEP_arch OF STEP IS
SIGNAL A0,A1,A2,B1,B2 :STD_LOGIC_VECTOR(15 downto 0):=(others=>'0');
SIGNAL Y2,Y1,X1,X2  :STD_LOGIC_VECTOR(15 downto 0):=(others=>'0');
SIGNAL mula,mulb  :STD_LOGIC_VECTOR(15 downto 0):=(others=>'0');
SIGNAL mulr    :STD_LOGIC_VECTOR(31 downto 0):=(others=>'0');
SIGNAL adda,addb,addr :STD_LOGIC_VECTOR(15 downto 0):=(others=>'0');
SIGNAL CNT    :STD_LOGIC_VECTOR(4 downto 0):=(others=>'0');
BEGIN
mull: lpm_mult
generic map(LPM_WIDTHA=>16,LPM_WIDTHB=>16,LPM_WIDTHS=>16,LPM_WIDTHP=>32,LPM_REPRESENTATION=>"signed",LPM_PIPELINE=>1)
port map(dataa=> mula,datab=> mulb,clock=> clk,result=> mulr);
adder1: lpm_add_sub
generic map(lpm_width=>16,LPM_REPRESENTATION=>"signed",lpm_pipeline=>1)
port map(dataa=>adda,datab=>addb,clock=> clk,result=>addr);
--Q15
A0  <=  "0000000000101010";--42      (0.00128)
A1  <=  "0000000001010000";--80      (0.00244)
A2  <=  "0000000000101010";--42      (0.00128)
B1  <=  "0111100101001000";--31048   (0.94754)
B2  <=  "1100011000010100";---14828  (-0.4525)
GEN:block
BEGIN
PROCESS(CLK_40n)
BEGIN
IF CLK_40n'EVENT and CLK_40n='1' THEN
 CNT <=CNT+"00001";
IF CNT="00000" THEN
 mula <=  A0;
 mulb <=  X0; 
ELSIF CNT="00010" THEN
 adda <=  mulr(30 downto 15);
 mula <=  A1;
 mulb <=  X1;
ELSIF CNT="00100" THEN
 addb <=  mulr(30 downto 15);
 mula <=  A2;
 mulb <=  X2;
ELSIF CNT="00110" THEN
 adda <=  addr;
 addb <=  mulr(30 downto 15);
 mula <=  B1;
 mulb <=  Y1;
ELSIF CNT="01000" THEN
 adda <=   addr;
 addb <=   mulr(30 downto 15);
 mula <=   B2;
 mulb <=   Y2;
ELSIF CNT="01010" THEN
 adda <=   addr;
 addb <=   mulr(30 downto 15);
ELSIF CNT="01100" THEN
 Yn <=   (addr(15) & addr(13 downto 0) & '0');
-- Yn1<=addr;
-- Yn2<=addr(14 downto 0) &'0'; -- the same with Yn
ELSIF CNT="01110" THEN
 Y1       <=  Yn;
 Y2       <=  Y1;
 X2       <=  X1;
 X1       <=  X0;
 CNT     <=  "00000";
END IF;
END IF;
END PROCESS;
END BLOCK GEN;
END STEP_arch; 

This is my testbench

LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_signed.all;
ENTITY Testbench_STEP IS
END Testbench_STEP;
ARCHITECTURE testbench_STEP_arch OF Testbench_STEP IS
component step
port(
 CLK, CLK_40n  :IN  STD_LOGIC:='0';
 X0 :IN STD_LOGIC_VECTOR(15 downto 0):=(others=>'0');
 Yn :BUFFER STD_LOGIC_VECTOR(15 downto 0):=(others=>'0')
 );
end component;
 
SIGNAL CLK, CLK_40n   : STD_LOGIC:='0';
SIGNAL X0    : STD_LOGIC_VECTOR(15 downto 0):=(others=>'0');
SIGNAL Yn    : STD_LOGIC_VECTOR(15 downto 0):=(others=>'0');
BEGIN
 
U: step port map (
  CLK  => CLK, 
  CLK_40n => CLK_40n,
  X0   =>  X0,
  Yn  =>  Yn
  );
 
tb: PROCESS
BEGIN
X0<= "0100000000000000";
loop
clk_40n <= '0' ; wait for 40 ns;
clk_40n <= '1' ; wait for 40 ns;
end loop;
END PROCESS;
END testbench_STEP_arch;