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Sangeetha2's avatar
Sangeetha2
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2 years ago
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Logic generation failed to load result from design analysis and cannot get the list of IPs in design

Facing error while I try to compile example design generated for JESD204B in Quartus Prime pro 23.2.

Logic generation failed to load results from design analysis and cannot get the list of IPs in the design.

For preset mode (LMF=222) also showing warnings while generating HDL.

Hdl
Platform

6 Replies

  • RichardT_altera's avatar
    RichardT_altera
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    2 years ago

    I do not see this error and able to pass the Analysis & Synthesis stage using Cyclone 10 GX.

    What device are you using? What is the setting that you used when generate the example design? Perhaps a screenshot and an example design attachment will help me to debug further.

    Also, could you check that you have the license activated for the JESD204B in the License Setup in Quartus. Or you can check in the license.dat file.

    Similar forum case on JESD204B license: https://community.intel.com/t5/Programmable-Devices/Purchasing-IP-license-for-Intel-JESD204B-IP-core/m-p/1462547

    Best Regards,

    Richard Tan

    p/s: If you find any answers from the community or Intel Support to be helpful, we encourage you to mark them as the best answer or rate them 4/5 in the survey.

    • Sangeetha2's avatar
      Sangeetha2
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      2 years ago

      Hi, thanks for the reply @RichardTanSY_Altera

      Since you have asked for the device and settings, I'm explaining in detail.

      I've tried to generate the example design for F-Tile JESD204B Intel FPGA IP, with existing preset mode(LMF=222) and tried compiling in Agilex 7 device (AGFB027R24C2E3VR2).

      But during the run of Analysis & Synthesis stage, there comes error in the support logic generation stage flashing the error message like "Logic generation failed to load results from design analysis and cannot get the list of IPs in the design"

      Also, I have the license activated for the JESD204B in the License Setup in Quartus.

      I'm attaching the snaps for your reference here.

  • RichardT_altera's avatar
    RichardT_altera
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    2 years ago

    I am able to pass the Analysis & Synthesis stage with the example design generated, using Agilex device.

    I will attached the design example and see if you can compile it from your side.

    If the design can't be compile, perhaps we might look into the OS you are using (whether it is supported) and uninstall & reinstall Quartus along with all the devices.

    Best Regards,

    Richard Tan

  • RichardT_altera's avatar
    RichardT_altera
    Icon for Super Contributor rankSuper Contributor
    2 years ago

    Do you able to run the example design, attached in my previous response?


    Best Regards,

    Richard Tan


    • Sangeetha2's avatar
      Sangeetha2
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      2 years ago

      Yes, the design what you have sent is running. Also, i tried generating the design in my colleague's system and copied the folder to mine. This design also compiling successfully.

      But when I try to generate and compile the example design in my system, it is failing.. Don't know what is the issue from my side.