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Sangeetha2's avatar
Sangeetha2
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2 years ago
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Logic generation failed to load result from design analysis and cannot get the list of IPs in design

Facing error while I try to compile example design generated for JESD204B in Quartus Prime pro 23.2. Logic generation failed to load results from design analysis and cannot get the list of IPs in th...
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RichardT_altera's avatar
RichardT_altera
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2 years ago

I am able to pass the Analysis & Synthesis stage with the example design generated, using Agilex device.

I will attached the design example and see if you can compile it from your side.

If the design can't be compile, perhaps we might look into the OS you are using (whether it is supported) and uninstall & reinstall Quartus along with all the devices.

Best Regards,

Richard Tan