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Sangeetha2
New Contributor
New ContributorLogic generation failed to load result from design analysis and cannot get the list of IPs in design
Facing error while I try to compile example design generated for JESD204B in Quartus Prime pro 23.2. Logic generation failed to load results from design analysis and cannot get the list of IPs in th...
Which OS are you running?
Could you check whether it is supported on the webpage below?
Perhaps you can update your system so that it aligns with your colleague's system.
At this point, it is hard for us to debug what's wrong, as we are not able to duplicate the issue.
Best Regards,
Richard Tan
RichardT_altera
Super Contributor
Super ContributorI am able to pass the Analysis & Synthesis stage with the example design generated, using Agilex device.
I will attached the design example and see if you can compile it from your side.
If the design can't be compile, perhaps we might look into the OS you are using (whether it is supported) and uninstall & reinstall Quartus along with all the devices.
Best Regards,
Richard Tan
