RichardT_alteraSuper ContributorJoined 6 years ago3294 Posts207 LikesLikes received198 SolutionsView All Badges
ContributionsMost RecentMost LikesSolutionsRe: QSYS Subsystem Export Port order Could you share a screenshot showing your expected result and the actual result? Is there any specific IP in the subsystem for which you want to change the order of the exported ports? For better understanding, could you also explain why you would like to define the order of the exported ports in a Platform Designer subsystem? Regards, Richard Tan Re: Quartus 20.1std compilation fails for Quartus map - Device 10AS057K2F40I1SG I don’t have any issues generating, even when changing the device to 10AS057K2F40I1HG. Both Linux and Windows OS are able to generate successfully. If possible, could you try using a different machine and see if the same issue occurs? Regards, Richard Tan Re: Quartus 20.1std compilation fails for Quartus map - Device 10AS057K2F40I1SG I suspect that you are not adding the HPS IP or making the connections correctly. Please refer to the GHRD design I shared to understand how to connect the HPS IP. Alternatively, try removing and re-adding the HPS IP in the top.qsys file. Regards, Richard Tan Re: Quartus 20.1std compilation fails for Quartus map - Device 10AS057K2F40I1SG Pasting the error here for reference and tracking: Warning: krpi_hps.arria10_hps_0: HPS model no longer supports simulation for HPS FPGA Bridges. Warning: krpi_hps.arria10_hps_0: This module has no ports or interfaces Info: Platform Designer Tip: Please Sync All System Infos before attempting to resolve the following error messages Error: krpi_hps.arria10_hps_0: Unsupported device 10AS057K2F40I1HG Error: krpi_hps: list element in quotes followed by ":" instead of space while executing "foreach {pad_id ball_name } $location_map { set pad_name "PAD_${pad_id}" set pad_to_ball_name($pad_name) $ball_name #send_message info " $pad_na..." (procedure "elab_io_interface_signals" line 36) invoked from within "elab_io_interface_signals $peripheral_name $mode_value peripheral_ports" (procedure "elab_FPGA_Peripheral_Signals" line 123) invoked from within "elab_FPGA_Peripheral_Signals $device_family" (procedure "elab" line 60) invoked from within "elab 1" (procedure "compose_logicalview" line 7) invoked from within "compose_logicalview" Error: krpi_hps.arria10_hps_0: "Counter for GPIO debouncer" (CONFIG_HPS_DIV_GPIO) 0 is out of range: 1-65535 Error: krpi_hps.arria10_hps_0: "Sugested peripherial PLL VCO frequency" (PERI_PLL_AUTO_VCO_FREQ) 0 is out of range: 320-3000 I do not see this error on my side. Could you confirm whether this error occurs during the Platform Designer Generate HDL process? I’ve attached a simple design for you to test it out. Regards, Richard Tan Re: Quartus Prime 25.1 Lite - Display Issues The GUI issue where the text appears to overlap for the ALTPLL is a known problem that has existed for some time. You can either use a Linux OS or instantiate it using HDL, as mentioned in another forum post shared by FvM. Unfortunately, the fix is still in progress because it involves a legacy IP. Regards, Richard Tan Re: State machine question in Arria X device Do you need further help regarding this case? Regards, Richard Tan Re: how to use design partition You may refer to the Design Block Reuse Flows in Section 1.5 of the Quartus Prime Pro Edition User Guide: https://docs.altera.com/r/docs/683247/25.1.1/quartus-prime-pro-edition-user-guide-block-based-design/answers-to-top-faqs In this flow, you (as the Developer) compile the B project and export a partition snapshot as B.qdb. You then create a black‑box file for module B. In the Consumer (top‑level) project A, the consumer adds the B black‑box file as a source in the project. After design elaboration, the consumer defines each instance of B as an independent design partition and assigns the exported B.qdb file to all B instances through the Design Partitions window. Regards, Richard Tan Re: SignalTap hover tooltip differs from waveform value (Quartus 23.1std.1) I have not seen this kind of issue before. Does it occur only with a specific design, or does it happen even with a small test design? Or perhaps specific node? Have you tried upgrading to Quartus 25.1 Standard to check whether the issue still occurs? If possible, please also try using a different machine. I would appreciate it if you could share the .stp file along with the data capture so that I can test it on my side. Regards, Richard Tan Re: Memory Mapped Interconnect Reset Net Polarity Conflict Let me know if further assistance is needed or if the solution worked for you. Regards, Richard Tan Re: The best way to implement SignalTapII Thank you, sstrell and FvM, for answering the question thoroughly. I couldn’t have explained it better myself. Regards, Richard Tan