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YZhou98's avatar
YZhou98
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28 days ago
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Shift Register Inference on Intel FPGAs – LUT-based Implementation Similar to Xilinx SRL?

Hello, I am trying to understand how Quartus implements shift registers on Altera FPGAs, and whether there is an equivalent mechanism to the LUT-based shift registers available on Xilinx devices (e.g...
Core Logic
Programmable Logic Device
  • FvM's avatar
    FvM
    26 days ago

    Hi,

    LUT based RAM is named MLAB RAM  in Altera FPGA. It's available with 6 input LUT logic elements, e.g. Cyclone V, Cyclone 10 GX, Arria 10, Agilex. It can be used to implement small RAM but apparently no shift registers.

    Regards Frank

YZhou98's avatar
YZhou98
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18 days ago

Thank you for the detailed information. I noticed that the synthesis tool does not infer deeper shift registers into MLAB or M20K when the RTL process includes a reset. However, when the shift-register process does not include a reset, the tool does infer them into memory blocks. Is this behavior always expected?

RichardT_altera's avatar
RichardT_altera
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16 days ago

Good observation — that behavior is expected.
Quartus will infer RAM‑based shift registers when the RTL is compatible with the device memory architecture. In particular, adding a reset to the shift chain typically prevents inference into MLAB/M20K and leaves the implementation in flip‑flops. The Quartus document below explicitly call out that coding styles like asynchronous resets can block RAM inference and force FF implementations:
https://docs.altera.com/r/docs/683641/25.3.1/quartus-prime-pro-edition-user-guide-design-optimization/guideline-remove-fitter-constraints?tocId=tmmzgVOTMhoEtv7TLENcLA

Additionally, on HyperFlex devices (Stratix 10 / Agilex), inference thresholds are higher to preserve Hyper‑Retiming. Checkout the KDB below: 
https://community.altera.com/kb/knowledge-base/why-doesnt-my-shift-register-get-inferred-when-targeting-intel%C2%AE-stratix%C2%AE10-fpga-/340793
 

Regards,
Richard Tan