It adds 3 and subtracts 1 instead of adding just 1

Hi!

I'm pretty new with vhdl and Quartus II and maybe this question is too obvious, but I spent three days on it and I cannot understand yet why is not working... I made a silly program, just adding one to a number, and just send one bit to the output. I tried to simulate it. There are no errors on Analysis & Synthesis, and no errors on EDA Netlist Writer. But the simulation is wrong (I don't obtain what I should)

1. I make a reset and "nombre" should be "0101010101", instead it is "0000000".

2. It should add 1 to this variable at each rising edge clock. Instead sometimes it adds 3 and then subtracts 1.

I cannot understand what's happening. I know it should be a really silly mistake from me, because this program is too simple, but I cannot find it. Moreover I've done a more complicated program and I had no problems. Can anybody help me, please?

Hier there is the code:

------------------------------------------------------------------------

library ieee;

use ieee.std_logic_1164.all;

use ieee.std_logic_arith.all;

use ieee.std_logic_unsigned.all;

library altera;

use altera.altera_primitives_components.all;

entity prova1 is

port

(

-- Input ports

clk : in std_logic;

reset : in std_logic;

-- Output ports

sortida : out std_logic

);

end prova1;

-- Library Clause(s) (optional)

-- Use Clause(s) (optional)

architecture arch_prova1 of prova1 is

signal nombre : std_logic_vector(9 downto 0):="0101010101";

begin

pr1: process(clk,reset,nombre)

begin

if reset='1' then

nombre<="0101010101";

else

if(rising_edge(clk)) then

nombre<=nombre+1;

else

nombre<=nombre;

end if;

end if;

end process pr1;

-- Add the library and use clauses before the design unit declaration

ff_sortida : DFF

port map (

d => nombre(4),

clk => clk,

clrn => not(reset),

prn => '1',

q => sortida

);

end arch_prova1;