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Altera_Forum
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17 years ago

It adds 3 and subtracts 1 instead of adding just 1

Hi! I'm pretty new with vhdl and Quartus II and maybe this question is too obvious, but I spent three days on it and I cannot understand yet why is not working... I made a silly program, just addi...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
17 years ago

if you write nombre <= nombre + 1; it is like C affectation.

The synthesizer want to 'wire' nombre with "nombre + 1". I think Quartus Synthesizer will introduce a DFF by itself on signal "nombre" if the process is synchronous and alert designer that nombre <= nombre + 1 were modified.

I use variable in process for edge detections for exemple.