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Altera_Forum
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17 years ago

It adds 3 and subtracts 1 instead of adding just 1

Hi! I'm pretty new with vhdl and Quartus II and maybe this question is too obvious, but I spent three days on it and I cannot understand yet why is not working... I made a silly program, just addi...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
17 years ago

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VHDL Process Statement warning at prova1.vhd(39): signal "nombre" is read inside the Process Statement but isn't in the Process Statement's sensitivity list

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because you have nombre <= nombre + 1;

I think it is better use variable which receive [b]nombre [/b] at clock edge.

var_nombre := nombre;

nombre <= var_nombre + 1;