It adds 3 and subtracts 1 instead of adding just 1

It's VHDL not C!

Variable command should never exist..

When you write VHDL you need to know exactly how it's been implemented.

Moreover the design works well and that's what is important.

If simulation is wrong it should be something about simulation signal or the reset condition not at 0.

Moreover simulation not guarantee that internal node that you see are what you expect (it depend on the implementation), but the output signal MUST be ok.

If you wanna see also the internal node right, the only solution is to route them as output too, but it's not important if you see the output signal right.

But please stop use "variable" or "integer".. it's not C.