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Altera_Forum
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17 years ago

It adds 3 and subtracts 1 instead of adding just 1

Hi! I'm pretty new with vhdl and Quartus II and maybe this question is too obvious, but I spent three days on it and I cannot understand yet why is not working... I made a silly program, just addi...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
17 years ago

An obvious reason to map the register polarity as found here, is in the fact, that many device families, e. g. Cyclone II and Cyclone III have no preset signal with DFF. The compiler has no other means to implement the logic at all. Thus the behaviour can't be changed by a setting or synthesis attribute.