Honored Contributor
Honored ContributorA variable must be used, if the assignment result has to take effect immediately, within the same clock cycle, e. g. if the variable is used as an interim result in other expressions and no pipelining is intended. Only in this case, there is a different behaviour of signal versus variable. If the variable value is used across clock cycles, a register is automaticly inferred by the compiler and it's behaving similar to a signal. This would be the case in the present code.
Using a variable, where no variable is required, can be regarded as bad programming style, but of course it's a matter of taste.
